Method of manufacturing a field effect transistor with optimized performances

ABSTRACT

The invention relates to a method for fabricating a field-effect transistor ( 1 ), comprising the steps of:
         providing a structure including a first layer of semiconductor material ( 102 ), a doped second layer of semiconductor material ( 103 ) arranged on top of the first layer of semiconductor material, the composition of which is different from that of the first layer ( 102 ), two spacers ( 120 ) made of dielectric material arranged on top of the second layer of semiconductor material ( 103 ) and separated by a groove ( 140 ), said second layer of semiconductor material being accessible at the bottom of said groove ( 140 );   etching the second layer of semiconductor material at the bottom of said groove until reaching said first layer of semiconductor material in such a way as to retain the first layer of semiconductor material beneath said spacers on either side of said groove ( 140 ); then   forming a gate stack ( 150 ) in said groove.

The invention relates to field effect transistors, and in particular tomethods for fabricating such transistors that are compatible withthree-dimensional integration methods.

To decrease the cost of integrated circuits and to increase theirperformance, manufacturers are constantly decreasing the size oftransistors, increasing the number thereof per chip, and increasing thenumber of circuits produced in parallel. To allow this increase in theperformance of integrated circuits, technologists are consequentlygeometrically decreasing the size of the transistors in the activeportion, along with the size of the interconnections. However,decreasing the technology node below 10 nm is problematic.

With a view to increasing integration density and/or decreasing thedistance between electronic components, it is known practice to carryout 3D integration by superposing a second active layer of electroniccomponents over the interconnect layer of a first active layer producedbeforehand.

In three-dimensional integration methods, any heating step in theformation of a second active layer over the intermediate interconnectlayer comes with a high risk of damaging the first active layer.

Doped source and drain formation generally requires dopant activationand the diffusion of these dopants at temperatures exceeding 1000° C.Such temperatures cannot be applied in the formation of the secondactive layer without damaging the first active layer.

A fabrication method has been proposed for decreasing the temperaturesapplied to activate dopants in a source or drain. According to such amethod, a layer of crystalline silicon that is not intentionally dopedis provided beforehand and arranged on top of a buried dielectric layer.A gate stack is formed on top of the layer of crystalline silicon.Spacers made of dielectric material are formed on either side of thegate stack. The upper portion of the silicon layer on either side of theassembly including the gate stack and the spacers is then amorphized.The amorphization method is carried out by means of ion bombardment.Next, dopants are introduced by ion implantation into the amorphoussilicon. A step of solid-phase recrystallization is then carried out ata temperature below 600° C. for the purpose of recrystallizing thesilicon layer and incorporating activated dopants into the crystallinestructure formed.

It is desirable to be able to dope the silicon layer as close aspossible up to the channel of the transistor to be formed, in particularto decrease access resistance. Thus, the silicon layer shouldadvantageously be doped beneath the spacers. Doping beneath the spacersin this way is relatively difficult to achieve and to control. Topromote greater proximity between the doped layer and the channel zone,one known method proposes producing very thin spacers beforehand oneither side of the gate stack. Ion implantation is then carried out asdescribed above on either side of the assembly including the gate stackand these thin spacers, then thicker spacers are formed over the thinspacers.

However, such a method has drawbacks. First, the zone beneath the verythin spacers cannot always be doped as desired. Second, the siliconlayer on top of the buried dielectric is generally very thin, generallyless than 9 nm thick. To be able to carry out the step ofrecrystallizing the silicon layer, it is necessary to retain crystallinesilicon at the interface with the buried dielectric after theamorphization step. With the thinness of the silicon layer, retainingcrystalline silicon in this way is difficult.

Additionally, the amorphization step results in the presence of residualdefects after recrystallization. Such residual defects may affect thecharacteristics of the transistor formed.

The invention aims to overcome one or more of these drawbacks. Thus, theinvention relates to a method for fabricating a field-effect transistorsuch as defined in the appended claims.

The invention also relates to the variants of the dependent claims. Aperson skilled in the art will understand that each of the features inthe description or in the dependent claims may be independently combinedwith the features of an independent claim without, however, constitutingan intermediate generalization.

Other features and advantages of the invention will become clearlyapparent from the description thereof that is given hereinafter, by wayof indication and without any limitation, with reference to the appendeddrawings, in which:

FIG. 1,

FIG. 2,

FIG. 3,

FIG. 4,

FIG. 5,

FIG. 6,

FIG. 7,

FIG. 8,

FIG. 9,

FIG. 10,

FIG. 11,

FIG. 12 and

FIG. 13 are sectional views of a field-effect transistor at varioussteps in its fabrication method according to a first embodiment;

FIG. 14 is a diagram illustrating the steps in the fabrication methodaccording to the first embodiment;

FIG. 15,

FIG. 16 and

FIG. 17 are sectional views of a field-effect transistor at varioussteps in its fabrication method according to a second embodiment;

FIG. 18 and

FIG. 19 are sectional views of a field-effect transistor at varioussteps in its fabrication method according to a third embodiment;

FIG. 20 is a perspective view of a field-effect transistor at a step ina fabrication method according to a fourth embodiment;

FIG. 21 is a perspective view of a field-effect transistor at anintermediate step in its fabrication method according to a fourthembodiment;

FIG. 22,

FIG. 23,

FIG. 24,

FIG. 25,

FIG. 26,

FIG. 27,

FIG. 28 and

FIG. 29 are sectional views of a field-effect transistor at varioussteps in its fabrication method according to the fourth embodiment;

FIG. 30 is a sectional view of a field-effect transistor at a step inits fabrication method according to a fifth embodiment.

FIGS. 1 to 13 are sectional views of a field-effect transistor 1 atvarious steps in its fabrication method according to a first embodiment.The diagram of FIG. 14 summarizes the steps in the fabrication methodaccording to the first embodiment. The invention may be implemented fromstep 308, starting from the configuration illustrated in FIG. 10.However, examples of prior steps with a view to obtaining theconfiguration illustrated in FIG. 10 will be described.

In step 300, a substrate provided with a layer 102 of semiconductormaterial, for example a silicon alloy, for example silicon that is notintentionally doped, is provided (the layer 102 described below will bemade of silicon that is not intentionally doped or of SiGe that is notintentionally doped). The thickness of the layer of silicon 102 isbetween 6 and 20 nm, for example 6 nm. The layer of silicon 102 is hereformed on top of a buried insulating layer 101, for example made of SiO₂(the layer 101 described below will be made of SiO₂). The thickness ofthe layer 101 is typically between 10 and 50 nm, for example 20 nm. Theburied insulating layer 101 is formed on top of a substrate 100, whichis typically made of silicon that is not intentionally doped (the layer100 described below will be made of silicon that is not intentionallydoped). The invention may however also be applied with a layer 102belonging to a bulk substrate.

In step 301, a layer 103 made of doped semiconductor material alloy isformed on top of the layer 102, as illustrated in FIG. 2. Thecomposition of the layer 103 is different from that of the layer 102.The doping of the layer 103 is in particular intended to improve theconduction properties between a channel zone and a source and drain ofthe transistor to be fabricated. The layer 103 is typically deposited byepitaxial growth on top of the layer 102. The thickness of the layer 103is typically between 2 and 10 nm. The layer 103 may be doped in situduring the epitaxial growth operation or by ion implantation later on.

The layer 103 is typically made of SiGe or silicon alloy. To form annMOS transistor, the doping of the layer 103 could be n-doping in alayer of silicon alloy. The n-type dopant is phosphorus, for example. Toform a pMOS transistor, the doping of the layer 103 could be p-doping ina layer of SiGe alloy. The p-type dopant is boron, for example. Thegermanium concentration of the layer 103 is for example between 15% and60% (in terms of number of atoms). The operation of deposition byepitaxial growth is for example carried out using SiGe with 30%germanium at a temperature of 630° C., using H₂ as the carrier gas, andgermane (GeH₄) and dichlorosilane (DCS, SiH₂Cl₂) as precursors. Theoperation of deposition by epitaxial growth may also be carried outusing SiGe with 10% germanium at a temperature of 700° C., using H₂ asthe carrier gas, and germane (GeH₄) and silane (SiH₄) as precursors.Advantageously, the layer 103 is pseudomorphic, i.e. its thickness isless than its critical thickness for relaxation, from which criticalthickness it begins to undergo plastic relaxation.

In steps 302 to 305, steps of fabricating a sacrificial gate areimplemented.

In step 302, a protective layer 104 is formed on top of the layer 103,as illustrated in FIG. 3. The layer 104 is typically made of SiO₂. Thethickness of this layer 104 is typically between 2 and 10 nm.

In step 303, a layer 105 made of amorphous silicon is formed on top ofthe protective layer 104, as illustrated in FIG. 4.

In step 304, a hardmask layer 106 is formed on top of the layer ofamorphous silicon 105, as illustrated in FIG. 5. The hardmask layer 106is for example formed of SiN. A layer of oxide, the thickness of whichis between 2 and 10 nm, may also be inserted between the layers 105 and106.

In step 305, a lithography step is carried out to form a hardmask in thelayer 106. Next, a step of anisotropically etching the layer 105 and thelayer 104 following the etch mask is carried out in order to form thesacrificial gate stack 110. The stack is etched down to the layer 103 inorder to obtain the configuration illustrated in FIG. 6.

In step 306, spacers 120 are formed on top of the layer 103, on eitherside of the sacrificial gate stack 110, in order to obtain theconfiguration illustrated in FIG. 7. The formation of the spacers 120may be implemented by conformal deposition of SiN, then byanisotropically etching this layer of SiN until the layer 103 isexposed. The width of the spacers 120 formed may for example be between5 and 10 nm.

In step 307, a raised source 131 and drain 132 are formed on top of thelayer 103, on either side of the assembly including the spacers 120 andthe sacrificial gate stack 110, in order to obtain the configurationillustrated in FIG. 8. The source 131 and the drain 132 are typicallyformed by epitaxial deposition of a silicon alloy on top of the layer103.

In step 308, a protective layer 107 is formed on top of the source 131and the drain 132, on either side of the assembly including the spacers120 and the sacrificial gate stack 110, in order to obtain theconfiguration illustrated in FIG. 9. The operation of forming theprotective layer 107 typically comprises an operation of depositingdielectric, typically based on SiO₂, followed by achemical-mechanical-polishing operation that stops at the hardmask ofthe sacrificial gate stack 110.

In step 309, the hardmask and the sacrificial gate stack 110 are removedto form a groove 140 between the spacers 120. The width of the groove140 thus obtained is advantageously at most equal to 40 nm. Theconfiguration illustrated in FIG. 10 is then obtained. This removaloperation is for example carried out by selective etching (with respectto the material of the spacers 120 and to the material of the protectivelayer 107 in particular) which stops at the layer 104. The layer 104 maythen be removed. The layer 103 is then accessible at the bottom of thegroove 140 and delimits the bottom of this groove 140. The etch may forexample be isotropic, by means of plasma etching.

In step 310 (which step may be carried out as a continuation of step309), the layer 103 is etched at the bottom of the groove 140 down tothe layer 102, stopping at this layer 102. The layer 102 may also beetched slightly. The configuration illustrated in FIG. 11 is thenobtained. The layer 102 is thus at least partly retained at the bottomof the groove 140 so as to be able to form a channel zone of thetransistor 1.

The flanks of the groove 140 are partly delimited by lateral faces ofthe etched layer 103, these lateral faces being aligned with innerlateral faces of the spacers 120. The doped portion of the accesses tothe channel zone, beneath the spacers 120, runsprecisely up to thischannel zone without encroaching onto this channel zone. The transistor1 thus formed exhibits decreased channel access resistance. Such resultsmay be obtained without requiring the prior formation of thinner spacerssurmounted by a new layer of spacers. To achieve the best possiblealignment between the lateral faces of the zone 103 and the lateralfaces of the spacers 120, the layer 103 is advantageouslyanisotropically etched.

In steps 311 and 312, the gate stacks 150 are formed. The stack mayinclude a gate insulator 108 over the lateral faces and over the bottomof the groove 140 (for example composed of a 0.5 to 2 nm stack of SiO₂surmounted by 3 to 5 nm of HfO₂) in order to obtain the configurationillustrated in FIG. 12. The gate insulator 108 is for example depositedby conformal deposition, by atomic layer deposition.

In step 312, the method moves on to forming a gate electrode 151 in thegroove 140 and over the gate insulator 108 in order to obtain theconfiguration illustrated in FIG. 13. The gate stack 150 is thus formed.The gate metal could for example be poly-Si or TiN. Other examples ofgate stacks are described in the document “the past, present and futureof high-k/metal gates”, in ECS Transactions, 53 (3) 17-26, published in2013, by Kisik Choi et al.

The steps of the method for fabricating the transistor 1 carried outaccording to the invention may have a thermal budget that issignificantly smaller than a step in which dopants are thermallyactivated. The steps in a method for fabricating a transistor 1according to the invention may thus be carried out without requiring adopant diffusion step to be carried out.

FIGS. 15 to 17 illustrate steps in a fabrication method according to asecond embodiment. The fabrication method according to the secondembodiment may be implemented starting from the configurationillustrated in FIG. 11 for the first embodiment. To obtain theconfiguration illustrated in FIG. 15, a step of depositing, by epitaxy,a layer of semiconductor material 160 on top of the layer 102 at thebottom of the groove 140 is carried out here. The layer of semiconductormaterial 160 is thus configured to be included within the channel zoneof the transistor. The semiconductor material 160 is for example siliconthat is not intentionally doped or silicon with a doping level that islower than that of the layer 103, when the layer 103 is made of siliconalloy. The semiconductor material 160 is for example an alloy of SiGethat is not intentionally doped or of SiGe with a doping level that islower than that of the layer 103, when the layer 103 is made of SiGealloy. The deposition operation 160 is advantageously carried out with athickness that is equal to that of the layer 103. The upper face of thedeposit 160 is advantageously aligned with the upper face of the layer103.

The layer of semiconductor material 160 may be designed to exhibitmechanical strain in a plane parallel to the layer 102. Thus, for a pMOStransistor, the layer 160 will advantageously be configured to exhibitcompressive strain (for example a layer 160 made of SiGe for a layer 102made of Si), while, for an nMOS transistor, this layer 160 could beconfigured to exhibit tensile strain (for example a layer 160 made of Sifor a layer 102 made of SiGe). Such mechanical strain allows themobility of carriers in the channel zone of the transistor 1 formed tobe increased.

To obtain the configuration illustrated in FIG. 16, a gate insulator 108is formed on the lateral faces and at the bottom of the groove 140. Thegate insulator 108 may be deposited with the same parameters as for step311.

To obtain the configuration illustrated in FIG. 17, the method moves onto forming a gate electrode 151 in the groove 140 and over the gateinsulator 108. The gate metal could for example be TiN or W.

FIGS. 18 and 19 illustrate steps in a fabrication method according to athird embodiment. The fabrication method according to the thirdembodiment may be implemented starting from the configurationillustrated in FIG. 7 for the first embodiment.

To obtain the configuration illustrated in FIG. 18, a step of etchingthe layer 103 on either side of the assembly including the sacrificialgate stack 110 and the spacers 120 is carried out.

To obtain the configuration illustrated in FIG. 19:

-   -   a raised source 131 and drain 132 are formed on top of the layer        102, on either side of the assembly including the spacers 120        and the sacrificial gate stack 110 (for example according to        parameters that are the same as those in step 307);    -   a protective layer is formed on top of the source 131 and drain        132, on either side of the assembly including the spacers 120        and the sacrificial gate stack 110 (for example according to        parameters that are the same as those in step 308);    -   the sacrificial gate stack 110 is removed to form a groove        between the spacers 120 (for example according to parameters        that are the same as those in step 309);    -   the layer 103 is etched at the bottom of the groove down to the        layer 102 (for example according to parameters that are the same        as those in step 310);    -   a gate insulator 108 is formed on the lateral faces and at the        bottom of the groove (for example according to parameters that        are the same as those in step 311);    -   a gate electrode 151 is formed in the groove and over the gate        insulator 108 (for example according to parameters that are the        same as those in step 312).

FIG. 20 is a perspective view of an example of a field-effect transistor2 at an intermediate step in its fabrication method according to afourth embodiment. FIGS. 21 to 29 are sectional views of the transistor2 at various steps in its fabrication method according to this fourthembodiment. The transistor 2 is here a finFET transistor, whichtypically has a gate facing three sides of a channel in the form of ananowire.

A structure provided with a substrate (not illustrated) surmounted by adielectric layer 201 is first provided. A nanowire 202 is formed on topof the layer 201.

The composition of the nanowire 202 is for example the same as that ofthe layer 102 described above. This nanowire 202 is encapsulated in alayer 203, the composition of which is for example the same as that ofthe layer 103 described above.

The layer 203 is typically deposited by epitaxial growth from thenanowire 202. The thickness of the layer 203 is typically between 2 and10 nm. Advantageously, the layer 203 is pseudomorphic, i.e. itsthickness is less than its critical thickness for relaxation, from whichcritical thickness it begins to undergo plastic relaxation.

The following steps in the method for fabricating the transistor 2 willbe illustrated by sectional views through the nanowire 202 along a planeparallel to the substrate of the structure.

In the configuration illustrated in FIG. 21, the following steps areimplemented:

-   -   conformal deposition of a protective layer 204 on top of the        layer 203. The protective layer 204 is typically made of SiO₂;    -   conformal deposition of a layer 205 of amorphous silicon on top        of the protective layer 204;    -   conformal deposition of a hardmask layer 206 on top of the layer        of amorphous silicon 205. The hardmask layer 206 is for example        formed of SiN.

In the configuration illustrated in FIG. 22, a lithography step has beencarried out. Next, a step of anisotropically etching the layer 206, thelayer 205 and the layer 204 is carried out in order to form asacrificial gate stack 210. The etch is stopped at the layer 203. Next,spacers 220 are formed on either side of the sacrificial gate stack 210in order to obtain the configuration illustrated in FIG. 22.

In the configuration illustrated in FIG. 23, a step of advantageouslyanisotropically etching the layer 203 is carried out in order to obtainthe element 213 beneath the assembly including the sacrificial gatestack 210 and the spacers 220. The etch is continued to remove thenanowire 202 on either side of the assembly including the sacrificialgate stack 210 and spacers 220 in order to obtain the configurationillustrated in FIG. 23.

In the configuration illustrated in FIG. 24, a raised source 231 anddrain 232 are formed on the nanowire 202, on either side of the assemblyincluding the spacers 220 and the sacrificial gate stack 210. The source231 and drain 232 are typically formed by epitaxial deposition on theexposed portion of the nanowire 202, for example deposition of a siliconalloy or an SiGe alloy (with for example a composition that isequivalent to that described with reference to the source 131 and drain132).

In the configuration illustrated in FIG. 25, a protective layer 207 isformed on top of the source 231 and the drain 232, on either side of theassembly including the spacers 220 and the sacrificial gate stack 210.

In the configuration illustrated in FIG. 26, the sacrificial gate stack210 has been removed to form a groove 240 between the spacers 220. Thisremoval operation is for example carried out by means of selectiveisotropic etching such that the element 213 then forms the bottom of thegroove 240.

In the configuration illustrated in FIG. 27, the layer 203 is etched atthe bottom of the groove 240 down to the layer 202, stopping at thislayer 202. The layer 202 is thus at least partly retained at the bottomof the groove 240 so as to be able to form a channel zone of thetransistor 2. The flanks of the groove 240 are partly delimited bylateral faces of the etched layer 203, these lateral faces being alignedwith lateral faces of the spacers 220. The doped portion of the accessesto the channel zone, beneath the spacers 220, runs precisely up to thischannel zone without encroaching onto this channel zone.

In the configuration illustrated in FIG. 28, the method moves on toforming a gate insulator 208 on the lateral faces and at the bottom ofthe groove 240. The gate insulator 208 could for example be SiO₂ or amaterial with a high dielectric constant such as HfOx.

In the configuration illustrated in FIG. 29, the method moves on toforming a gate electrode 251 in the groove 240 and over the gateinsulator 208. A gate stack 250 is thus formed. The gate metal could forexample be the same as that used for the gate electrode 151.

FIG. 30 is a sectional view of a field-effect transistor 2 at anintermediate step in its fabrication method according to a fifthembodiment. The fabrication method according to the fifth embodiment maybe implemented starting from the configuration illustrated in FIG. 27for the fourth embodiment. To obtain the configuration illustrated inFIG. 30, a step of depositing, by epitaxy, a layer of semiconductormaterial 260 on top of the layer 202 at the bottom of the groove 240 iscarried out here. The layer of semiconductor material 260 is thusconfigured to be included within the channel zone of the transistor. Thesemiconductor material 260 is for example silicon that is notintentionally doped or silicon with a doping level that is lower thanthat of the layer 203, when the layer 203 is made of silicon alloy. Thesemiconductor material 260 is for example an alloy of SiGe that is notintentionally doped or of SiGe with a doping level that is lower thanthat of the layer 203, when the layer 203 is made of SiGe alloy. Thedeposition operation 260 is advantageously carried out with a thicknessthat is equal to that of the layer 203. The upper face of the deposit260 is advantageously aligned with the upper face of the layer 203.Method steps that are similar to those described with reference to FIGS.28 and 29 may then be carried out.

1. A method for fabricating a field-effect transistor, the methodcomprising: providing a structure comprising a first layer ofsemiconductor material; forming a second layer, which is a doped layerof semiconductor material on top of the first layer, a composition ofthe second layer being different from a composition of the first layer;forming a sacrificial gate, and two spacers made of a dielectricmaterial that are arranged on top of the second layer, the sacrificialgate being arranged between the spacers; removing the second layer oneither side of an assembly formed by the sacrificial gate and thespacers; removing the sacrificial gate to form a groove separating thespacers, the second layer being accessible at a bottom of the groove;etching the second layer at the bottom of the groove until reaching thefirst layer in such a way as to retain the first layer beneath thespacers on either side of the groove; and forming a gate stack in thegroove.
 2. The method according to claim 1, wherein the first layer ismade of silicon alloy.
 3. The method according to claim 2, wherein thefirst layer is made of silicon that is not intentionally doped.
 4. Themethod according to claim 2, wherein the second layer is made of SiGe orsilicon alloy.
 5. The method according to claim 3, wherein, prior to theforming the gate stack in the groove, the method further comprises:depositing, by means of epitaxy, a third layer of an alloy of siliconthat is not intentionally doped or with a doping level that is lowerthan a doping level of the second layer on top of the first layer at thebottom of the groove.
 6. The method according to claim 5, wherein thethird layer is made of SiGe.
 7. The method according to claim 5, whereinthe third layer is deposited with a thickness that is identical to athickness of the second layer of silicon alloy present beneath thespacers.
 8. The method according to claim 1, wherein the etching thesecond layer is carried out by an anisotropic etching.
 9. The methodaccording to claim 1, wherein the forming the gate stack comprisesdepositing a gate dielectric on top of the first layer exposed at thebottom of the groove.
 10. The method according to claim 1, wherein: themethod further comprises: depositing, by means of epitaxy, a siliconalloy above the first layer on either side of the assembly.
 11. Themethod according to claim 1, wherein a thickness of the second layer ofthe structure provided is between 2 and 5 nm.
 12. The method accordingto claim 1, wherein a width of groove is at most equal to 40 nm.
 13. Themethod according to claim 1, wherein the forming the second layer iscarried out by depositing, by means of epitaxy, a layer of dopedsemiconductor material on top of the first layer so as to form thesecond layer.